CIRCUIT FOR CONTROLLING EQUALIZATION PULSE WIDTH

摘要

PURPOSE: An equalization pulse width controlling circuit is provided which forms an appropriate equalization pulse width for securing data stability and minimizing delay of operation speed. CONSTITUTION: An equalization pulse width controlling circuit includes a pulse generator(100) for forming a predetermined pulse width according to a set option when an address signal shifts, and an adder(200) for adding up the pulse formed at each address. The circuit further has a latch(300) for latching an equalization signal in enable state when a normal Y select signal and a redundancy Y select signal are both enabled using a signal enabling the redundancy Y select signal.