| 摘要 |
<p>A filter arithmetic device comprising horizontal half pixel motion compensation and horizontal in-loop filter means (100) which is provided with first pixel delay means (200), second pixel delay means (201), multiplying means (202), left shifting means (203), first selecting means (204), adding means (205), second selecting means (206), selection control signal generating means (207), third pixel delay means (208), right shifting means (209), and shift amount control means (210). Such a filter arithmetic device having a horizontal processing unit and a vertical processing unit both for half pixel motion compensation and in-loop filtering of inputted pixel data can, for example, have an arithmetic unit shared by both the horizontal and vertical processing units and have a reduced hardware scale.</p> |
