| 摘要 |
PURPOSE: A processor duplexing device of communication system is provided to reduce the buffer delay in record/read for the memory of a standby operated processor and the standby time of the processor by properly proceeding intermediation for the memory with the standby operated processor. CONSTITUTION: A central processing unit(101,201) controls overall operations of board according to active operation mode or standby operation mode. A buffer control unit(102,202) controls the states of data and address buffer operations according to the operation mode of the central processing unit(101,201). A first data buffer(103,203) and a second data buffer(104,204) are enabled according to the control of the buffer control unit(102,202) and buffer data. A third data buffer(105,205) buffers the data transmitted from the opposite board. A first address buffer(106,206) and a second address buffer(107,207) buffer addresses from the central processing unit(101,201). A third address buffer(108) transmits the addresses from the frist address buffer(106) to the opposite board. A DRAM(109,209) records the opposite data from the third data buffer(105), An SRAM(110,210) is connected to the central processing unit(101,201), and records all data to maintain the standby state. |
