发明名称 MULTILAYER METAL LINE SUBSTRATE AND METHOD FOR FABRICATING THE SAME
摘要 PURPOSE: A multilayer metal line substrate and a method for fabricating the same are provided to implement fine line width with simple processes by inserting a ceramic connector such as conductive layers into holes to realize electrical connection. CONSTITUTION: A first metal line layer(12) is formed on a first substrate(11) except a first hole. A first insulating film(13) is formed on the first metal line layer(12) adjacent to the first hole. A first plating layer(17) is formed on the exposed first metal line layer(12) and on the side of the first insulating film(13) adjacent to the first hole(15). A second substrate(11a) having a second hole(16a) greater than the first hole(15) is formed on the first insulating film(13). A second metal line layer(12a) is formed on the second substrate(11a). A second insulating film(13a) is formed on the second metal line layer(12a) adjacent to the second hole(16a). A second plating layer(17a) is formed on the exposed second metal line layer(12a) and on the sides of the second insulating film(13a) adjacent to the second hole(15a). A first/second conductive layers(19,19a) are respectively formed within the first/second holes(16,16a).
申请公布号 KR100259081(B1) 申请公布日期 2000.06.15
申请号 KR19980006398 申请日期 1998.02.27
申请人 HYUNDAI MICRO ELECTRONICS CO., LTD. 发明人 KANG, DAE-SOON
分类号 H01L21/28;(IPC1-7):H01L21/28 主分类号 H01L21/28
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