发明名称 |
Method and apparatus for estimating internal power consumption of an electronic circuit represented as netlist |
摘要 |
This is a method of quickly computing the power dissipated by a digital circuit using information available at the gate library level. It estimates the short-circuit power by modeling the energy dissipated by the cell per input transition as a function of the transition time or edge rate, and multiplying that value by the number of transitions per second for that input.
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申请公布号 |
US6075932(A) |
申请公布日期 |
2000.06.13 |
申请号 |
US19970949676 |
申请日期 |
1997.10.14 |
申请人 |
SYNOPSYS, INC. |
发明人 |
KHOUJA, ADEL;KRISHNAMOORTHY, SHANKAR;MAILHOT, FREDERIC G.;MEIER, STEPHEN F. |
分类号 |
G06F17/50;(IPC1-7):G06F17/50 |
主分类号 |
G06F17/50 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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