发明名称 Technique for reducing peak current in memory operation
摘要 A circuit in a memory device and a method for precharging at least one bit line in the memory device. The circuit includes a primary precharger and a secondary precharger in communication with the bit line. The secondary precharger gradually precharges the bit line before the primary precharger precharges the bit line between memory operations.
申请公布号 US6075733(A) 申请公布日期 2000.06.13
申请号 US19980198062 申请日期 1998.11.23
申请人 LSI LOGIC CORPORATION 发明人 BROWN, JEFF S.
分类号 G11C7/12;(IPC1-7):G11C7/00 主分类号 G11C7/12
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