| 摘要 |
A hardware-based system for configuring a CPU and chip set logic of a computer system to allow data transfers on both the rising and falling edges of a bus clock signal. The CPU and chip set logic each include bus communication circuitry for transferring data, a storage unit, and a configuration circuit. The contents of the storage unit determine whether the respective bus communication circuitry transfers data on only one or on both clock edges. Initially, the bus communication circuits transfer data on only one clock edge. The configuration circuits of the CPU and chip set logic are connected by a single signal line and participate in a serial exchange of signals over the single signal line. The configuration circuits modify the contents of the respective storage units dependent upon an outcome of the serial exchange of signals. The configuration circuit of the CPU initiates the exchange of signals, transmitting a query signal. Upon receiving the query signal, the chip set logic configuration circuit transmits a response signal and modifies the contents of the chip set logic storage unit such that the chip set logic bus communication circuitry transfers data on both clock edges. Upon receiving the response signal from the chip set logic, the CPU configuration circuit modifies the contents of the CPU storage unit such that the CPU bus communication circuitry transfers data on both clock edges. As a result, data transfers on both clock edges are implemented within the computer system.
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