| 摘要 |
A circuit is disclosed herein which generates the sum of two numbers (A and B) and the sum plus 1 in parallel so as not to take any additional time to generate the sum plus 1 value. The circuit comprises a carry look-ahead (CLA) tree portion and a summer portion. The CLA tree portion generates carry bits, as well as the logical relationship Ai +E,ovs XOR+EE Bi, for application to a summer for bit position i. The carry bits contain information for either inverting or not inverting the Ai +E,ovs XOR+EE Bi bit for both the sum and the sum plus 1 output of the summer. The sum bit and sum plus 1 bit are generated at approximately the same time.
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