发明名称 |
Multimedia computer architecture with multi-channel concurrent memory access |
摘要 |
A computer system providing multiple processors or masters an architecture for highly concurrent processing and data throughput. A multiple channel memory architecture provides concurrent access to memory. Arbitration and snoop logic controls access to each memory channel and maintains cache coherency. A host CPU, multimedia processor, pipes processor and display controller may independently and concurrently access memory. The pipes processor provides a decoupled input/output processor for universal serial bus and firewire serial buses to free up the host CPU.
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申请公布号 |
US6076139(A) |
申请公布日期 |
2000.06.13 |
申请号 |
US19970940914 |
申请日期 |
1997.09.30 |
申请人 |
COMPAQ COMPUTER CORPORATION |
发明人 |
WELKER, MARK W.;BONOLA, THOMAS J.;MORIARTY, MICHAEL P. |
分类号 |
G06F12/02;G06F12/08;G06F12/10;G06F13/16;G09G5/39;(IPC1-7):G06F13/16 |
主分类号 |
G06F12/02 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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