High performance cost optimized memory with delayed memory writes
摘要
A memory device includes an interconnect with control pins and bidirectional data pins. A memory core stores data. A memory interface circuit is connected to the interconnect and the memory core. The memory interface circuit includes a delay circuit to establish a write delay during a memory core write transaction such that the memory core write transaction has a processing time that is substantially equivalent to a memory core read transaction. The delay circuit delays the memory core write transaction for a time corresponding to the time required for signals to travel on the interconnect.
申请公布号
US6075730(A)
申请公布日期
2000.06.13
申请号
US19980169729
申请日期
1998.10.09
申请人
RAMBUS INCORPORATED;INTEL CORPORATION
发明人
BARTH, RICHARD M.;WARE, FREDERICK A.;STARK, DONALD C.;HAMPEL, CRAIG E.;DAVIS, PAUL G.;ABHYANKAR, ABHIJIT M.;GASBARRO, JAMES A.;NGUYEN, DAVID;HOLMAN, THOMAS J.;ANDERSON, ANDREW V.;MACWILLIAMS, PETER D.