| 摘要 |
The object of the present invention is to eliminate, in a data processing system having multiple buses, a combination of devices that can not be accessed via a PCI to PCI bridge. When an access request is issued to an S-ISA device by an S-PCI device, a PCI to PCI bridge determines whether or not a requested address is outside a blocked area, and whether or not the address matches an address stored in a retry register. When the requested address does not match the address in the retry register, the PCI to PCI bridge mistakes the access request for an access to a P-PCI device. Thus, the PCI to PCI bridge positively decodes the access request on the S-PCI bus, and transmits an access request on the P-PCI bus. However, since none of the P-PCI devices do not decode the request, the PCI to PCI bridge has to terminate the bus cycle on the P-PCI bus by master abort. At this time, the PCI to PCI bridge stores the requested address in the retry register, and terminates the bus cycle on the S-PCI bus in the retry manner. Following this, although the S-PCI device tries again to access the S-ISA device, the PCI to PCI bridge refers to the address in the retry register and does not decode the access request. Since none of devices on the S-PCI bus positively decodes the access request, the PCI to ISA bridge subtractively decodes the request. As a result, the access request is transmitted to the S-ISA bus, and the S-ISA device can decode this request, thereby establishing a correct bus cycle.
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