| 摘要 |
<p>The invention concerns a chip card (CA) receiving fields of compressed data encapsulated in frames including an indication of the expected length of decompressed data and a length of compressed data. The frames are received in a storage unit (MC) and the processor (PR) of the card decompresses each data field according to a decompression algorithm over a length based on the indication of the expected length and writes the decompressed data in another buffer storage unit (MD). Several algorithms and optionally several decompression models are installed in the card storage unit (MS), and a couple thereof is selected by the number read in the heading of each frame received.</p> |
