Information processing system

摘要

A Triple Modular Redundancy (TMR) unit 10 comprises a plurality of processors connected by a bus and simultaneously executing the same processing operation. One of the processors is a master processor and the remaining processors are slaves. Information formed only by the master processor is outputted to the bus. Each processor has a multiplex control circuit 48 which compares the output information formed by the respective processor with the information outputted to the bus, thereby detecting a failure and allowing an internal circuit 46 to execute necessary processes. Various aspects of the TMR unit are described, but the claims relate to using an existence processor display flag circuit (340, Fig. 27A) indicating which processor(s) is/are normally operating among the plurality of processors constructing the multiplex unit and which processor(s) is/are disconnected from the multiplex unit due to a failure or the like.