| 发明名称 |
Slotted damascene lines for low resistive wiring lines for integrated circuit |
| 摘要 |
<p>A process of forming a wiring in a semiconductor interlayer dielectric, includes simultaneously patterning a via and a slotted line in the interlayer dielectric, simultaneously etching the via and the slotted line, and simultaneously filling the via and the slotted line with a metal. <IMAGE></p> |
| 申请公布号 |
EP1006572(A1) |
申请公布日期 |
2000.06.07 |
| 申请号 |
EP19990309539 |
申请日期 |
1999.11.29 |
| 申请人 |
SIEMENS AKTIENGESELLSCHAFT;INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
BRONNER, GARY B.;COSTRINI, GREG;RADENS, CARL J. |
| 分类号 |
H01L21/768;H01L23/522;(IPC1-7):H01L21/768 |
主分类号 |
H01L21/768 |
| 代理机构 |
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代理人 |
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| 主权项 |
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| 地址 |
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