Multilayer wiring board

摘要

A multilayer wiring board (5) for mounting a semiconductor chip or a semiconductor device (4), in which the number of wiring layers (5a, 5b, 5c, 5d) is minimized to provide improved product yield, product reliability and production cost. Each wiring layer (5a, 5b, 5c, 5d) includes lands (8) arranged in the form of a square lattice and wiring patterns (7) each having one end connected to one of the lands (8) and the other end extending outward beyond an outermost row of the lattice. The lands (8) have a land pitch p and a land diameter d and the wiring patterns (7) have a pattern width w and an interpattern space s, wherein p, d, w and s satisfy the following relationship: $and\; Furthermore,\; the\; lattice\; has\; periodic\; land-free\; or\; vacant\; lattice\; sites\; (20),\; all\; lands\; (8)\; in\; the\; outermost\; row\; have\; wiring\; patterns\; (7)\; extending\; outward\; therefrom,\; and\; the\; land-free\; or\; vacant\; lattice\; sites\; (20)\; provide\; a\; space\; through\; which\; wiring\; patterns\; (7),\; which\; are\; connected\; to\; lands\; (8)\; of\; an\; inner\; row,\; pass\; through.\mathop{\mathrm{image}}$