| 摘要 |
A sync signal is inserted to a signal modulated by RLL (1,7), thereby forming one sector. One cluster is formed by 16 sectors, a preamble, and a postamble. Further, DSV control bits are inserted to data after the modulation. A frequency of recording data concerning the bit number of one cluster after the DSV control bits were inserted is equal to 8.817984 MHz. A frequency of a read clock of the physical address which is previously recorded on an optical disk is equal to 24.192 kHz. By dividing a frequency of 17.635968 MHz into 1/2, a clock signal of a frequency equal to the channel bit frequency can be formed. By dividing it into 1/729, a clock signal of a frequency of a read clock can be formed.
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