| 摘要 |
A method and apparatus for constructing a digital phase differentiator incorporating a dynamic decrement counter (30). A limited signal is sampled at a fixed sampling rate. A fixed rate for an intermediate frequency is obtained. The fixed sampling rate is divided by a divisor to obtain a frequency of a clock. The frequency of the clock is divided by the intermediate frequency to obtain an desired average divider. A set of integer load values (34, 36 and 38) is selected that on average yields a non-integer value that is close to the desired average divider. A load of the dynamic decrement counter (30) changes cyclically using the set of integer load values (34, 36 and 38) to obtain a phase of the limited signal.
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