发明名称 DRY ETCHING METHOD
摘要 PROBLEM TO BE SOLVED: To provide a dry etching method for preventing a deterioration in interlayer breakdown strength in a wiring structure, and realizing a minute pattern of the wiring structure while the performance is not decreased even though an etching apparatus in a conventional SAC process in a semiconductor manufacturing process is used. SOLUTION: In a dry etching method, an etching gas is fed to a reactive chamber and the etching is carried out by making the etching gas in a plasma state. As for the etching gas, an additive gas of NOx is added to a main gas containing C and F to use a mixed etching gas. When the interlayer film 7 is etched in a SAC manufacturing step, a selective ratio with a stopper of Si3M4 film 6 can be increased, and when a wiring layer 10 is formed, interlayer breakdown strength with a gate electrode 3 can be made sufficiently well.
申请公布号 JP2000156366(A) 申请公布日期 2000.06.06
申请号 JP19980329780 申请日期 1998.11.19
申请人 SONY CORP 发明人 YAMANE TETSUYA
分类号 H01L21/302;H01L21/28;H01L21/3065;H01L21/3213;(IPC1-7):H01L21/306;H01L21/321 主分类号 H01L21/302
代理机构 代理人
主权项
地址