| 摘要 |
A voltage generating circuit for a semiconductor memory cell using a complementary MOS (CMOS) circuit uses an external clock signal on behalf of an internal oscillator clock signal as an input signal for driving an electric charge pumping portion, and performs a pumping operation which actively corresponds to the external input environment. The voltage generating apparatus includes: a frequency dividing circuit which reduces a frequency when the frequency of an external clock signal is too fast, and generates a reduced frequency; a frequency doubling portion which increases a frequency when the frequency of an external clock signal is too slow, and generates an increased frequency; a switch and delay portion which receives the external clock signal and an output signal of a level sensing portion, is controlled by the output signal of the level sensing portion, transmits the external clock signal to an electric charge pumping portion, cuts off or delays a transmission of external clock signal; an electric charge pumping portion which outputs a high voltage or a bulk bias voltage; and a reference electric potential sensing portion which senses an electric potential of the output terminal of the electric charge pumping portion, and thus controls the switch and delay means. As a result, the voltage generating apparatus reduces a chip area and a power-consumption, thereby facilitating a test of the voltage generating circuit.
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