Method for simultaneously fabricating a DRAM capacitor and metal interconnections

摘要

A method for simultaneously forming a storage node and a plurality of interconnection in fabricating a semiconductor device on a substrate. The method comprises the steps of: forming a first dielectric layer over said cell array area and said periphery; forming a plurality of first contact holes through said first dielectric layer in said cell array area and said periphery area, said periphery area including a bitline and a word line, said word line and said bitline being used for addressing said memory cell; forming a first conductive layer in said plurality of first contact holes and on said first dielectric layer; patterning and etching said first conductive layer to form said storage node and said plurality of interconnections simultaneously; forming a second dielectric layer and a second conductive layer subsequently on said first dielectric layer, said storage node and said plurality of interconnections; and patterning and etching said second dielectric layer and said second conductive layer to form a charge storage means and a plurality of contact plugs.