| 摘要 |
PROBLEM TO BE SOLVED: To generate higher-speed clock edges than the period of testing rate generation continuously even in a simple hardware scale. SOLUTION: A rate generating circuit 1 receives a signal A to generate a clock C and timing data B. A shift circuit 3 receives the input of the timing data B, shifts it by a set number of stages, and outputs timing data D. Conversion memory 4 outputs variable delay setting data E to be inputted to variable delay circuits in oscillation circuits 5A and 5B with the timing data D as an input address. An oscillation control circuit 6 outputs enabling signals F1 and F2 to oscillate the oscillation circuits 5A and 5B alternately. The oscillation circuits 5A and 5B starts oscillation by the oscillation enabling signals F1 and F2 and is capable of changing oscillation frequency. A logical sum gate 7 obtains the sum of oscillation clocks G1 and G2 and generates high-speed clock edges H continuously.
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