| 摘要 |
PURPOSE: A semiconductor memory device is provided to reduce dimension thereof and power consumed by a clock signal and data shift blocks, and to stabilize an operating state by lowering noise. CONSTITUTION: A semiconductor memory device(201) comprises a pad block(251), a first and a second I/Os(241, 242), a delay locked loop circuit(243), an interface logic(231) and a data shift block(261). The pad block(251) with many pads is located between a first memory bank(211) and a second memory bank(221). Data is transferred between the I/Os(241, 242) and outside through the pad block(251). The delay locked loop circuit(243) stabilizes a frequency of an external clock signal inputted through the pad block(251) and generates an internal clock signal. The interface logic(231) controls the memory banks(211, 221) and the I/Os(241, 242) by being synchronized with the internal clock signal. The data shift block(261) is located adjacent to the upper end or the lower end of the pad block(251) and synchronized with the internal clock signal. Data is transferred between the I/Os(241, 242) and the data shift block(261) through a first and a second wiring groups and between the memory banks(211, 221) and the data shift block(261) through a third and a fourth wiring groups. The third and the fourth wiring groups have n times as many wiring as the first and the second wiring groups.
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