| 摘要 |
PURPOSE: A synchronous SRAM circuit is provided to be operated with clock signals of short cycle and thereby increase frequency. CONSTITUTION: An address decorder (50) receives external address signals (Add) from an address register (1), receives burst mode signals (BMS) from a controller (3), and generates internal address signals. An enable counter (40) in burst mode counts block coding signals (ANI_I, ANO_I) inputted from the address decorder (50) and outputs coding signals (COS). A plurality of cell data outputted via plural sense amplifiers (71-74) are inputted to a multiplexor (100). The multiplexor (100) outputs one of the plurality of input cell data in accordance with the coding signals (COS). A plurality of cell data are latched at a time, so that the latched cell data can be outputted by synchronizing with fast clock.
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