| 摘要 |
PURPOSE: A clock generation circuit is provided to improve clock generation in a CDMA receiver for easy error corrections of frequency wave and phase in the CDMA receiver. CONSTITUTION: An RF signal and an output of an IF frequency wave mixer (90) are inputted to an RF down converter (80). The RF down converter (80) outputs an IF signal, which is inputted to an ADC (analog-digital converter; 100). An output of the ADC (100) is inputted to a CDMA demodulator (110). An AFC (automatic frequency wave control signal) is inputted to an integrator (70), to which a PWM (pulse wave modulation control signal) as well as the AFC is inputted. An output of the integrator (70) is inputted to a VCTCXO (voltage control-type crystal oscillator circuit; 50). An output of the VCTCXO (50) is simultaneously inputted to the IF frequency wave mixer (90) and a base band clock generator (60). An output of the base band clock generator (60) is inputted to the ADC (100) and the CDMA modulator (110).
|
