| 摘要 |
PURPOSE: A phase and frequency detector for a high speed phase locked loop is provided to shorten the reset path necessary to descend a terminal output to a low state, thereby minimizing noises affecting the high speed phase locked loop and at the same time, improving an operating frequency. CONSTITUTION: A phase and frequency detector for detecting a phase and frequency difference between a basic signal applied to a high speed phase locked loop and an oscillation signal oscillated from the loop. The detector includes a first latch means (410), which latches a basic signal and outputs it to a first output terminal, and a second latch means (420), which latches an oscillation signal and outputs it to a second output terminal. An input signal intercepting means (430) receives the basic signal and the oscillation signal and when the first and second latch means are in a reset state, prevents the basic and oscillation signals, a signal level of which is presently in change, from being outputted. A reset signal generation means (440) generates a reset signal by receiving the basic signal and the oscillation signal. The first latch means (410) and the second latch means (420) are reset by a first reset means (450) and a second reset means (460), respectively, in accordance with the reset signal.
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