发明名称 METHOD FOR ISOLATING ELEMENT OF COMPLEMENTARY MOS TRANSISTOR
摘要 PURPOSE: A method is provided to selectively reinforce any region of an element isolation region between a well region and an activated region. CONSTITUTION: A first mask pattern is formed to expose a first element isolation region isolating each activated region in first and second regions(100P,100N) and to expose a second element isolation region isolating an n-type well region and a p-type well region. And, a first trench(140B) having first depth in the first isolation region and a second trench(140C) having the same depth in the second isolation region are formed by etching a semiconductor substrate(100) with a first mask pattern as an etch mask. Then, a second mask pattern is formed to expose the second trench after eliminating the first mask pattern. The depth of the second trench is made to have second depth deeper than the first depth by etching the semiconductor substrate with the second mask pattern as the etch mask. Therefore, the device of a complementary MOS(metal oxide semiconductor) transistor is isolated.
申请公布号 KR20000030938(A) 申请公布日期 2000.06.05
申请号 KR19980043699 申请日期 1998.10.19
申请人 SAMSUNG ELECTRONICS CO., LTD. 发明人 LEE, YEONG HYEON;DOH, MYEONG GEUN
分类号 H01L21/76;(IPC1-7):H01L21/76 主分类号 H01L21/76
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