| 摘要 |
PURPOSE: An input/output circuit for a high speed DRAM cell is provided to save power, which is consumed at a cell, by exciting only a bit line selected at a Y-decoder. CONSTITUTION: An input/output circuit for a high speed DRAM includes a plurality of cellblocks(46,47) each having data. The data of the cell blocks(46,47) are read by a bit line pull-up block(45) exciting bit lines(BL,BBL) connected to the cells of the cell blocks(46,47). A bit line pull-up control block outputs control signals for controlling the bit line block(45) according to ATDSUM signals generated by detecting Y-decoding signals, Z-addresses, and MAT selection signals. An X-decoder(43) enables word lines of the cell blocks(46,47). A Y-decorder enables columns of the sell blocks(46,47). A column selection control part(44) selects a column according to the enable signals of the Y-decoder(42).
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