| 摘要 |
<p>An integrated circuit chip having an optimum size for its circuit scale is provided while eliminating pad necks. The integrated circuit chip comprises a substrate (1), which includes circuit modules (6, 7, 8), and I/O terminals (2, 4) for coupling signals to the circuit module (6, 7, 8). The I/O terminals (2) are used to couple operating signals to and from the circuit modules (6, 7, 8) while the I/O terminals (4) are used to test the circuit modules (6, 7, 8). The I/O terminals (2) are arranged along the border of the substrate (1), and the I/O terminals (4) and the circuit modules (6, 7, 9) are arranged inside the I/O terminals (2) on the substrate. The I/O terminals (2) are connected with leads (12) through bonding wires (14), and the I/O terminals (4) are not connected with the leads (12).</p> |
