| 摘要 |
In overall operation, in order to perform a Q15 multiply together with a Q31 accumulate operation, the processing proceeds as follows: Initially the Q15 values form the register bank (8) are read out upon bus A and bus B and fed as inputs to the single cylce integer multiplier (16). The result, which is in Q30-like form, is fed back to the register bank (8). On a subsequent processsing cycle one of the new instructions is executed (e.g. a QDADD instruction) to read out the Q30-like result of the multiply on the A bus and the Q31 accumulate value on the B bus. The Q30-like value is then left shifted by one or saturated by the shifting and saturating unit (26) and supplied as one input to the arithmetic logic unit (22). |
