Insulated gate type semiconductor device with potential detection gate for overvoltage protection

摘要

Internal gate electrodes (71) are all connected in common to a gate terminal, and a floating gate electrode (72) is connected to the gate electrode of an NMOS transistor (M1). An external emitter electrode (91) is provided on a first major surface of P-type diffused lease region (21), and N-type diffused emitter region (31) and P-type diffused base region (21) are short-circuited. The source of the NMOS transistor (M1) and an emitter terminal are also connected to the external emitter electrode (91). The drain of the NMOS transistor (M1) is connected to an external terminal.