发明名称 DIGITAL AMPLITUDE LIMITING AMPLIFYING CIRCUIT, METHOD THEREFOR AND DIGITAL DEMODULATOR
摘要 PROBLEM TO BE SOLVED: To reduce a memory capacity which becomes necessary when a large gain is to be obtained. SOLUTION: A shift bit number detection part 7 detects the number of bits where '0' continues from a higher order that eliminates a sign bit out of inputted N bit amplitude data as a shift bit number. P channel/Q channel for correctly demodulating phase modulated signal (PCH/QCH) bit shift parts 5 and 6 convert the data into an M bit smaller than the N bit by bit shifting the N bit amplitude data only for the number of shift bits. Thus, it is possible to attain miniaturization of a circuit by reducing a memory capacity which is needed to be stored in the PCH/QCH amplitude restriction amplifier memories 51 and 52 beforehand.
申请公布号 JP2000151729(A) 申请公布日期 2000.05.30
申请号 JP19980314822 申请日期 1998.11.05
申请人 NEC CORP 发明人 KOMABA TAKEO
分类号 H04L27/22;H04L27/227 主分类号 H04L27/22
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