| 摘要 |
PROBLEM TO BE SOLVED: To enable effective test of a memory device by connecting each control line to data lines, connecting such data line to one of the bit line pair, and selectively driving the data line to a first voltage level of the high logical level and to a second voltage level of the low logical level for the loading of the voltage level to the bit line. SOLUTION: The transistors 23A to 23B of the test circuit 20 connect each bit line of bit line pair to the transistors 24A or 24B of the transistor rows 23A and 23B of the test circuit 20 for all bit line pairs 2 connected to the transistor 8 in the transistor row 7A. Owing to the relationship of the transistor row 7A of the bit line control device 1, transistor rows 23A and 23B of the test circuit 20 and bit line pairs 2A and 2D, the test vector written into the memory array 5 can be tested quickly. A detection circuit 26 generates a detected voltage level on the output life 80.
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