CAS LATENCY TIME CONTROL CIRCUIT

摘要

PROBLEM TO BE SOLVED: To provide a CAS latency time control circuit for preventing a data delay brought about when data pass an unnecessary latch means. SOLUTION: A data path-selecting part 25 is connected between a second latch means 23 and a third latch means 24 so that data is transmitted directly to the third latch means 24 without passing a first and the second latch means 22 and 23 at a first and a second CAS latency time operations. A fourth latch means which operates with the third latch means 24 may be prepared, whereby data is directly input to an input of the fourth latch means, and outputs of the third latch means and fourth latch means are selectively output.