发明名称 Scalable receiver structure for efficient bit sequence decoding
摘要 Synchronization words, contained within a data transmission are detected by oversampling the incoming data transmission by a factor of M. Each of M samples are stored in a respective register on an ongoing basis and a receiver is activated to monitor the contents of all registers to determine if they contain a synchronization word. Commonly a plurality of registers may detect the presence of a synchronization word simultaneously. The one having the largest amplitude bit samples is selected and the receiver changes mode to monitor the output of that register while another receiver is activated to monitor all registers. This is particularly useful in detecting synchronization words or flags in data packets, particularly in modem to modem communications.
申请公布号 US6069928(A) 申请公布日期 2000.05.30
申请号 US19970885803 申请日期 1997.06.30
申请人 CIRRUS LOGIC, INC. 发明人 GUPTA, SANJAY
分类号 H04L7/04;(IPC1-7):H04L7/00 主分类号 H04L7/04
代理机构 代理人
主权项
地址