发明名称 |
Interrupt capture and hold mechanism |
摘要 |
A processor is provided with an interrupt capture and hold mechanism. In one embodiment, a processor includes an instruction pipeline having stages for executing instructions. In the event of an exception, the instructions in the pipeline are flushed or aborted. This requires that each stage in the pipeline receive and respond to an exception-causing signal. An interrupt is an exception causing signal which may be provided by circuitry external to the processor. To ensure that such a signal is asserted long enough for each stage in the pipeline to receive and respond to it, all external hardware interrupts are routed through an interrupt capture and hold mechanism, thereby advantageously preventing the causation of an undefined processor state with little added complexity.
|
申请公布号 |
US6070218(A) |
申请公布日期 |
2000.05.30 |
申请号 |
US19980007913 |
申请日期 |
1998.01.16 |
申请人 |
LSI LOGIC CORPORATION |
发明人 |
GILES, CHRISTOPHER M.;ECKNER, HARTVIG |
分类号 |
G06F9/38;G06F9/48;(IPC1-7):G06F9/46 |
主分类号 |
G06F9/38 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|