| 摘要 |
A Dynamic Random Access Memory (DRAM) configurable by eight (x8) or by nine (x9). The DRAM has nine Data Input/Outputs (I/Os). The memory array is divided into two or more sub-arrays, with sub-array cells arranged in addressable rows and columns. When the DRAM is configured x8, one I/O is held in its high impedance state; one ninth of the DRAM's data path (between the array and the ninth I/O) is ignored; and, the entire array address space is available for data storage through eight I/Os. When the DRAM is configured x9, all nine I/Os are active; the DRAM I/O path is reconfigured with part of the array providing the ninth bit through the ninth I/O; and the array address space reduced by one-eighth. All nine bits may be from a common sub-array. Alternatively, sub-arrays may be paired so that when the DRAM is configured x9, eight bits are accessed in seven-eighths of one sub-array, with the ninth bit being accessed in one eighth of the other sub-array of the pair.
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