| 摘要 |
PROBLEM TO BE SOLVED: To provide a semiconductor storage device the chip size of which is prevented from becoming larger by making its wiring and element areas smaller and which is reduced in power consumption and suitable for a DDRSDRAM(double data rate synchronous DRAM). SOLUTION: A data pad row P is formed by arranging a train of data pads 1, 2,..., n in a straight line and a plurality of data latch circuits 21 which latch signals from the data pads is arranged in an area 20 between two straight line 11 and 12 which are drawn through both ends of the pad row P perpendicularly to the row P. The wiring lengths between the data latch circuits 21 and an internal clock generating circuit 23 are made equal to each other and, at the same time, the wiring lengths from initial-stage circuits (DIN) 31 to the data latch circuits 21 are matched to the wiring lengths from the internal clock generating circuit 23 to the data latch circuits 21 and the circuits 31, 21, and 23 are operated with a voltage 24 obtained by dropping the voltage of external power supply. |
