发明名称 METHOD FOR SETTING THRESHOLD VOLTAGE OF MOS TRANSISTOR AND SEMICONDUCTOR DEVICE
摘要 PROBLEM TO BE SOLVED: To set threshold voltage with ease and precision. SOLUTION: In pMOSs 18 and 20, a source region 30 consists of a p+ source region 34 and an LDD region 36 consisting of p-, and a drain region 32 comprises a p+ drain region and an LDD region 40 consisting of p-. The pMOSs 18 and 20 contain hallow layers 42 and 44 consisting of an n-type conductive layer at facing parts of the LDD regions 36 and 40. The pMOSs 18 and 20 are different from each other in the quantity of impurity implantation into the hallow layers 42 and 44, and in the set value of threshold voltage.
申请公布号 JP2000150885(A) 申请公布日期 2000.05.30
申请号 JP19990246564 申请日期 1999.08.31
申请人 SEIKO EPSON CORP 发明人 TAKAMURA TAKASHI
分类号 H01L29/78;H01L21/8234;H01L27/088;(IPC1-7):H01L29/78;H01L21/823 主分类号 H01L29/78
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