发明名称 Semiconductor memory device having voltage booster circuit
摘要 An equalizing circuit is connected between a pair of bit lines. The equalizing circuit is made up of three MOS transistors and an equalization control signal is supplied to the gates of the MOS transistors. A sense amplifier circuit is connected to the bit lines. The sense amplifier circuit amplifies the potential difference occurring between the bit lines, for the detection of data. The equalization control signal is output from a level conversion circuit. An internal boosted voltage-generating circuit constantly generates a boosted voltage which is higher than an externally-applied power supply voltage applied to a power supply terminal. The boosted voltage is applied to the level conversion circuit. The level conversion circuit converts an input control signal, whose high-level voltage is equal to, or lower than the externally-applied power supply voltage, into the boosted voltage, thereby generating the equalization control signal.
申请公布号 US6069828(A) 申请公布日期 2000.05.30
申请号 US19980108264 申请日期 1998.07.01
申请人 KABUSHIKI KAISHA TOSHIBA 发明人 KANEKO, TETSUYA;OHSAWA, TAKASHI
分类号 G11C11/409;G11C5/14;G11C7/12;G11C8/08;G11C11/407;G11C11/4094;(IPC1-7):G11C7/12 主分类号 G11C11/409
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