PULSE SYNCHRONIZING CIRCUIT

摘要

PROBLEM TO BE SOLVED: To minimize a circuit structure and also improve a transfer efficiency by generating a synchronizing pulse by a logical sum of outputs signals of a second D-FF and a third D-FF and using its synchronous pulse as an asynchronous reset signal of the D-FF with asynchronous reset. SOLUTION: A delay gate 100 is connected to a clock input terminal CLK of a D-FF with asynchronous reset 101. A D1 is a pulse signal synchronized with a clock signal CLK1 of a high speed clock and a pulse signal D1 inputs to each of an input terminal of the delay gate 100 and a data input terminal D of the D-FF101 with asynchronous reset. Also, an output signal CD from the delay gate 100 inputs to the clock input terminal CLK of the D-FF with asynchronous reset 101. Also, a data input terminal D of a D-FF102 is connected to an output terminal Q of the D-FF101 with asynchronous reset.