发明名称 |
SOI STRUCTURE HAVING REDUCED PARASITIC CAPACITANCE AND PRODUCTION THEREOF |
摘要 |
PROBLEM TO BE SOLVED: To reduce parasitic capacitance by forming a doped region directly adjacent to an isolation layer in an underlying silicon substrate using a dopant having a conductivity opposite to that of a silicon substrate. SOLUTION: In general, an isolation layer 104 is a buried oxide layer just like an SOI structure 1100. An active semiconductor layer 102 normally contains doped N type or P type silicon and has active and passive circuit elements and an interconnecting contact region. The isolation layer 104 is formed in a substrate 10. In several embodiments, the isolation layer is formed of sapphire or other dielectric material 104. A doped layer 210 (or region) is formed in a substrate 106 contiguously to the isolation layer 104. When the substrate 106 has P type conductivity, the doped layer 210 has N type conductivity.
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申请公布号 |
JP2000150841(A) |
申请公布日期 |
2000.05.30 |
申请号 |
JP19990316316 |
申请日期 |
1999.11.08 |
申请人 |
NATL SEMICONDUCTOR CORP <NS> |
发明人 |
DARMAWAN JOHAN;OLGAARD CHRISTIAN;LEE TSUNG WEN |
分类号 |
H01L27/12;H01L21/761;H01L21/762;H01L27/08;(IPC1-7):H01L27/12 |
主分类号 |
H01L27/12 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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