发明名称 JIG AND METHOD FOR PERFORMING BURN-IN TEST ON SEMICONDUCTOR DEVICE
摘要 PROBLEM TO BE SOLVED: To provide a jig and method for performing burn-in test on semiconductor device by which the deformation of solder balls can be suppressed when burn-in tests are performed on a semiconductor device, even when eutectic solder is used for securing the mountability of the semiconductor device. SOLUTION: A jig for performing burn-in test on semiconductor device comprises a substrate 2 which is interposed between a semiconductor device 7 and an anisotropic conductive sheet 4, and contact sections 3 which are integrally formed with the substrate 2 through the substrate 2 and are made of a conductive material and into which ball grids 8 are inserted. The jig is constituted in such a way that the ball grids 8 are pressed against the electrode sections 5 of the conductive sheet 4 through the contact sections 3.
申请公布号 JP2000150591(A) 申请公布日期 2000.05.30
申请号 JP19980336473 申请日期 1998.11.12
申请人 NEC CORP 发明人 MATSUOKA HIROSHI
分类号 H01L21/60;G01R31/26;H01L21/66;(IPC1-7):H01L21/60 主分类号 H01L21/60
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