| 摘要 |
PROBLEM TO BE SOLVED: To keep a jitter amount of a transmission side data signal within a tolerance and to prevent erroneous operation in data transmission by always detecting the jitter amount and switching a frequency for phase comparing at a digital PLL when the detected jitter amount exceeds the tolerance. SOLUTION: A threshold for indicating a tolerance is set to a jitter detection threshold setting part 21. A jitter detection signal generation part 19 detects a jitter between a reception side clock signal 4 and a transmission side clock signal 12. A comparator 20 compares an output 22 of the jitter detection signal generation part 19 with an output 23 of the jitter detection threshold setting part 21 and outputs an output signal 29 for indicating whether the jitter amount is within or outside the tolerance. When a clock selection part 27 indicates that the output signal 29 is outside the tolerance, it activates a control part 28. The control part 28 sets a value in which the jitter amount is within the tolerance out of predetermined plural kinds of frequency multiplication rates. |
