发明名称 MEMORY CELL FOR DEFECT RELIEF AND STORAGE DEVICE UTILIZING THE SAME
摘要 PROBLEM TO BE SOLVED: To provide a memory cell for defect relief capable of being composed of redundant cells of the less number even when an ECC(error detecting/ correcting circuit) is used. SOLUTION: When an ECC is used in a multilevel memory, the least significant bit data (8 bits) in each cell includes, in redundant memory cells (4 bits), information indicating whether a defect exists or not as well as positional information of the defect, while more significant bit data (the bit data other than the least significant bit data) (8 bits) include, in a redundant memory cell (1 bit), only information indicating whether a defect exists or not. Since the more significant redundant memory cells only require 1 bit, the redundant memory cells of only 3 bits are required by storing, in the more significant redundant memory cells, information indicating whether a defect exists or not as well as positional information of the defect with respect to the least significant bit data.
申请公布号 JP2000149592(A) 申请公布日期 2000.05.30
申请号 JP19980319696 申请日期 1998.11.11
申请人 NEC IC MICROCOMPUT SYST LTD 发明人 NAKAMURA YOSHIHIRO
分类号 G11C17/00;G11C16/02;G11C16/04;G11C16/06;G11C29/00;G11C29/42 主分类号 G11C17/00
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