发明名称 Digital slew rate and duty cycle control circuit and method
摘要 A signal shaping circuit for use in a transmission line driver and the like is disclosed. The input is pulse signal having a rising edge that triggers a delay circuit which produces a first sequence of multiple delayed outputs and a falling edge which triggers the delay circuit to produce a second sequence of multiple delayed outputs. Transition control circuitry is included which operates to control the transition time of the output signal in a first direction, such as the rise time, in response to the first sequence of multiple delayed outputs and to control the transition time of the output signal in a second direction, such as the fall time, in response to the second sequence of multiple delayed outputs. By controlling the first and second delayed output, the rise and fall times of the output signal can be precisely controlled.
申请公布号 US6069511(A) 申请公布日期 2000.05.30
申请号 US19980140091 申请日期 1998.08.26
申请人 NATIONAL SEMICONDUCTOR CORPORATION 发明人 MOHAN, JITENDRA
分类号 H03K5/00;H03K5/13;(IPC1-7):H03K3/017;H03K5/04;H03K7/08 主分类号 H03K5/00
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