发明名称 SEMICONDUCTOR MEMORY DEVICE
摘要 <p>PROBLEM TO BE SOLVED: To lower consumption power and stabilize an operation by providing a first switch for electrically shutting one of a pair of bit lines, a second switch for electrically shutting the other bit line, and a third and a fourth switches connected to the first and second switches in series for shutting the bit lines respectively. SOLUTION: When an address signal is input, an array part A100 is selected and switch elements SW110 and SW111 set to a corresponding bit line precharge means BPC100 and switch elements SW130 and SW131 set to a main sense node precharge means MPC100 are turned off. A word line WL0 is driven and a potential difference is brought about between a pair of bit lines BL and BLb and between a pair of presense nodes PS100 and PS101. A preamplifier part PSA100 is activated to transfer the potential difference to the pair of the presense nodes PS100 and PS101.</p>
申请公布号 JP2000149567(A) 申请公布日期 2000.05.30
申请号 JP19980317341 申请日期 1998.11.09
申请人 OKI ELECTRIC IND CO LTD 发明人 TANOI SATOSHI;OKADA ATSUHIKO
分类号 G11C11/419;G11C7/06;G11C11/409;G11C11/4091;G11C16/06;(IPC1-7):G11C11/409 主分类号 G11C11/419
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