发明名称 DIGITAL SYSTEM
摘要 PROBLEM TO BE SOLVED: To carry out stable fast operation by verifying the timing margin of an actual electric circuit and setting optimum timing conditions according to the result when the system is started. SOLUTION: An electric timing optimizing circuit 1 supplies a clock CLKa to a circuit A 2 and a clock CLKb to a circuit B 3. An optimum condition decision circuit 101 sets all timing conditions that a circuit block possibly has in a timing condition setting circuit 102 one by one, verifies whether or not the circuit block operates normally under the set timing conditions, and sets a center timing condition among timing conditions wherein the circuit block does not operate normally in respective circuit blocks. The timing condition setting circuit 102 generates a signal for controlling a timing generating circuit 103, which adjusts the skew between circuit blocks.
申请公布号 JP2000148575(A) 申请公布日期 2000.05.30
申请号 JP19980315502 申请日期 1998.11.06
申请人 PFU LTD 发明人 MATSUOKA MASANARI;YOSHIMOTO SATORU;MATSUNAGA HIROYUKI
分类号 G06F12/16;G06F11/24;G06F12/00 主分类号 G06F12/16
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