FERRO-DIELECTRIC MEMORY DEVICE INCLUDING ON-CHIP TEST CIRCUIT

摘要

PROBLEM TO BE SOLVED: To enable on-chip test by arranging a non-volatile memory cell at the intersecting point of a first bit line and a word line, sensing a voltage difference between the second bit line corresponding to the first bit line and first and second bit lines, and supplying a variable test voltage to any one of the first and second bit lines depending on a control signal supplied from the external circuit. SOLUTION: When the performance margin test of capacitors provided in the arrays 10, 12, 20 and 22 is requested, an on-chip test circuit 40 supplies a voltage VDMP-T/VDMP-B varied from the external side to the bit lines BL1-T-BLi-T or BL1-B-BLi-B. The test circuit 40 controls a row decoder circuit 26 to non-activate the second reference cell array 22 and then supplies the variable voltage to the bit lines BL1-B-BLi-B as the reference voltage. A low performance capacitor can be removed by evaluating the performance margin of a ferro-dielectric capacitor.