| 摘要 |
PROBLEM TO BE SOLVED: To reduce cost of a test for, and improve the reliability of, a dynamic RAM or the like which comprises a plurality of banks and an interface circuit. SOLUTION: A dynamic RAM or the like comprises a plurality of banks, main amplifiers MAU and MAL of a predetermined number for simultaneously performing a writing or readout operation of stored data for memory cells of a predetermined number in a specified bank, and an interface circuit IF for transmitting and receiving in parallel the stored data between the MAU and MAL. An ECC circuit ECC is further provided for detecting and correcting a bit error in the stored data M0-M127 of, for example, 128 bits to be transmitted and received between the main amplifiers MAU and MAL, and the interface circuit IF. Test output signals TD, each being of 1 bit and indicating that syndromes S0-S8 of, for example, 9 bits to be generated from the ECC circuits ECC, or all of their bits, exhibit a logical value of '0', are stored in the interface circuit IF in total of, e.g. 128 bits, and are output via, e.g. 16 data input/ output terminals in a packet style of 16×8 bits.
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