| 摘要 |
PROBLEM TO BE SOLVED: To provide a memory device for shortening access times when a CPU continuously reads data from a memory. SOLUTION: A burst cycle detecting circuit 7 is connected between a CPU 2 and a memory control circuit 5, a burst address generating circuit 6 is connected between the CPU 2 and an address multiplex circuit 4, and a data holding circuit 32 is connected between a memory 1 and an error detecting and correcting circuit 31. Thus, when the CPU reads data in a burst cycle, access times can be shortened since the next data are read during error detection or/and a correcting operation.
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